Tuesday, February 6, 2018
2 step Column Parallel Delta Sigma ADC
2 step Column Parallel Delta Sigma ADC
CentraleSupelec, France, publishes a paper "A 14-b Two-step Inverter-based ?? ADC for CMOS Image Sensor" by Pierre Bisiaux, Caroline Lelandais-Perrault, Anthony Kolar, Philippe Benabes, and Filipe Vinci dos Santos presented at IEEE International NEWCAS Conference, in June 2017 at Strasbourg, France.
"This paper presents a 14-bit Incremental Sigma Delta (I??) analog-to-digital converter (ADC) suitable for a column wise integration in a CMOS image sensor. A two-step conversion is performed to improve the conversion speed. As the same ?? modulator is used for both steps, the overall complexity is reduced. Furthermore, the use of inverter-based amplifiers instead of operational transconductance amplifier (OTA) facilitates the integration within the column pitch and decreases power consumption. The proposed ADC is designed in 0.18 �m CMOS technology. The simulation shows that for a 1.8 V voltage supply, a 20 MHz clock frequency and an oversampling ratio (OSR) of 70, the power consumption is 460 �W, achieving an SNR of 83.7 dB."
